RadiSys ATCA-5400 RTM Specifikace stáhnout pdf (Strana 55)

CPM resets

TheCPMsupportsonlycoldandpowergoodresets.Anywarmresetsourcesareconverted

toacoldresetbythe legacyFPGA.

Cold reset

Acoldresetisatotalsystemboardreset(ex ceptfortheIPMIcircuitry).Alldevicesand

registersareresettotheirdefaultstate.Afteracoldreset,datainDRAMmightbeinvalid

duetotheCPUmemorycontrollerdiscontinuingrefreshcycles.Memoryisthencleared

duringthesystemBIOSinitialization.

Note:AcoldresetontheCPMdoesnotclearthestickybitsintheCPUandI/Ohub

registers.Clearingstickybitsrequiresapowergoodreset.SeePowergoodresetfordetails.

Commoncausesofacoldresetincludeexpirationofthewatchdogtimerinterval,

invocationoftheFRUControlIPMIcommandwiththeColdResetoption,andcontrolby

theuser’sownapplicationsoftwarerunningontheprocessor.Table 13liststhesources

thatcaninitiateacoldresetandtheresultantactions.

Powergood reset

Apowergoodre setissimilartoacoldreset,exceptthatallstickybitsintheCPUandI/O

hubregistersarealsocleared.ApowergoodresetcanbeinitiatedbytheBIOSoruser

applicationbywriting0EhtotheCF9hresetregisterontheICH10R.

Note:Apowergoodreset

shouldonlybeusedwhenthestickybitsneedtobecleared.

Table 13. Cold reset sources

Cold Reset Source Action

Watchdog 1 timeout IPMC asserts SYS_RESET* (low). See BMC watchdog.

“FRU Control (Cold Reset) IPMI command” IPMC asserts SYS_RESET* (low). See Supported IPMI commands on

page 97.

IPMC Corrupt Flash Watchdog expires IPMC asserts SYS_RESET* (low) and drives FLASH_SEL to select the

alternate SPI flash. The IPMC then de-asserts SYS_RESET* (high) to allow

the CPM to attempt to boot from the alternate flash. See Corrupt flash

detection watchdog.

CPU XDP emulator reset CPU XDP port asserts SYS_RESET* (low)

06h written to Reset Control register (CF9h) ICH asserts PLTRST* (low)

Pushbutton reset is asserted The CPU complex FPGA asserts SYS_RESET* (low).

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RadiSys ATCA-5400 RTM Specifikace Strana 55