RadiSys ATCA-5400 RTM Specifikace Strana 37

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4
USB controller
37
USB controller
TheICHcontainstwouniversalhostcontrollerinterface(UHCI)controllersandtwo
enhancedcontrollerhostinterface(EHCI)controllersthatsharethesamesetofpins.Each
pairofcontrollersprovidesuptotwelveUSB1.1orUSB2.0ports.EachEHCIportallows
datatransfersupto480Mb/sandreportsovercurrentstatusbacktotheICH.
TheCPMprovidesthefiveportslistedinTable 6whenconfiguredforEHCI(USB2.0):
SATA controller
TheICHincludestwoSATAhostcontrollersthatsupportdatatransferratesofupto3.0
Gbps.CommunicationovertheSATAbuscanoperateinoneoftwodifferentmodes,
dependingonoperatingsystemrequirements:
•Innativemode,bothcontrollersareusedtoimplementuptosixSATAports.Ports0‐3
arehandledbythefirstcontrollerandports4‐5arehandledbythesecondcontroller.
•Inlegacymode,onlyports0‐3areavailablefromthefirstcontroller.
ForinformationaboutSAS/SATAswitchingcontrol,refertoSASandSATAonpage 39.
SPI bus
TheICHusesaserialperipheralinterface(SPI)busforcommunicationwiththetwoboot
flashdevices.ThisconnectionisdiscussedinmoredetailunderRedundantbootflash.
LPC bridge
TheICHenablescommunicationbetweentheCPUandlowbandwidthperipheralsby
providingalowpincount(LPC)bridgeconnectiontothefollowingdevices:
•SuperI/O(seeSuperI/Ochip)
•CPUcomplexFPGA(seeCPUcomplexFPGA)
•IPMC(seeIntelligentPlatformManagementController)
TheLPCbridgeimplementsallofthecyclesdescribedintheIntelLowPinCountInterface
Specification,Revision1.1.
Table 6. USB 2.0 ports
Port Number Port Location Notes
0 Front panel, upper USB port Refer to Front panel connectors on page 26 for additional
information.
1 Front panel, lower USB port
2 No external port connections USB NAND flash A and B. User flash is discussed under
Redundant user flash.
3
4 RTM USB port Refer to Rear transition module (RTM) interface on page 29.
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